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publication# 080152 rev : g amendment: /0 issue date: october 1999 am79r79 ringing subscriber line interface circuit distinctive characteristics ideal for short-loop applications ideal for isdn terminal adaptor and fixed radio access applications on-chip ringing with on-chip ring-trip detector low standby state power battery operation: ?v bat1 : ?40.5 v to ?75 v ?v bat2 : ?19 v to v bat1 on-chip battery switching and feed selection on-hook transmission two-wire impedance set by single external impedance programmable constant-current feed programmable open circuit voltage programmable loop-detect threshold current gain = 1000 ground-key detector tip open state for ground-start lines polarity reversal option available internal v ee regulator (no external ?5 v power supply required) two on-chip relay drivers and snubber circuits (32 plcc) block diagram e1 d2 d1 two-wire interface hpa hpb input decoder and control relay driver ring-trip detector power-feed controller rtrip1 rtrip2 bgnd vcc vneg rd rdc agnd/dgnd vbat2 a(tip) b(ring) ryout1 rdcr c1 switch driver vbat1 rsgl ground-key detector off-hook detector relay driver ryout2 c2 c3 rsgh b2en rsn vtx signal transmission ringin rye det
2 am79r79 data sheet general description the legerity family of subscriber line interface circuit (slic) products provide the telephone interface func- tions required throughout the worldwide market. leger- ity slic devices address all major telephony markets including central office (co), private branch exchange (pbx), digital loop carrier (dlc), fiber-in-the-loop (fitl), radio-in-the-loop (ritl), hybrid fiber coax (hfc), and video telephony applications. the legerity slic devices offer support of borsht (battery feed, overvoltage protection, ringing, supervi- sion, hybrid, and test) functions with features including current limiting, on-hook transmission, polarity reversal, tip open, and loop-current detection. these features allow reduction of linecard cost by minimizing compo- nent count, conserving board space, and supporting automated manufacturing. the legerity slic devices provide the two- to four-wire hybrid function, dc-loop feed, and two-wire supervision. two-wire termination is programmed by a scaled imped- ance network. transhybrid balance can be achieved with an external balance circuit or simply programmed using a companion legerity codec device, the am79c02/03/ 031 dslac? device, the am79q02/021/03 program- mable quad slac (qslac?) device, or the am79q5457/4457 nonprogrammable qslac device. the am79r79 ringing slic device is a bipolar mono- lithic slic that offers on-chip ringing. now designers can achieve significant cost reductions at the system level for short-loop applications by integrating the ring- ing function on chip. examples of such applications would be isdn terminal adaptors, fiber-in-the-loop, ra- dio-in-the-loop, hybrid fiber/coax and video telephony (home-side) boxes. the am79r79 ringing slic can provide sufficient voltage to meet the stringent lssgr five-ringer equivalent specification. using a cmos- compatible input waveform and wave shaping r-c net- work, the am79r79 ringing slic can provide trapezoi- dal wave ringing to meet various design requirements. in order to further enhance the suitability of this device in short-loop, distributed switching applications, leger- ity has maximized power savings by incorporating bat- tery switching on chip. the am79r79 ringing slic device switches between two battery supplies such that in the off-hook (active) state, a low battery is used to save power. in order to meet the open circuit voltage requirements of fax machines and maintenance termi- nation units (mtu), the slic automatically switches to a higher voltage in the on-hook (standby) state. like all of the legerity slic devices, the am79r79 ringing slic device supports on-hook transmission, ring-trip detection, programmable loop-detect thresh- old, and is available with on-chip polarity reversal. the am79r79 ringing slic device is a programmable con- stant-current feed device with two on-chip relay drivers to operate external relays. several performance grades are available to meet both ccitt and lssgr require- ments, including various longitudinal balance options. this unique device is available in the proven legerity 75 v bipolar process in the 32-pin plcc package.
am79r79 data sheet 3 ordering information standard products note: * functionality of the device from 0c to +70c is guaranteed by production testing. performance from ?40c to +85c is guaranteed by characterization and periodic sampling of production units. am79r79 j c temperature range c = commercial (0c to 70c)* package type j = 32-pin plastic leaded chip carrier (pl 032) device number/description am79r79 jc valid combinations ?1 performance grade option ?1 = 52 db longitudinal balance, polarity reversal ?2 = 63 db longitudinal balance, polarity reversal ?3 = 52 db longitudinal balance, no polarity reversal ?4 = 63 db longitudinal balance, no polarity reversal valid combinations ?1 ?2 ?3 ?4 valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availabil- ity of specific valid combinations, to check on newly released combinations, and to obtain addi- tional data on legerity?s standard military?grade products. legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below am79r79 ringing subscriber line interface circuit
4 am79r79 data sheet connection diagram top view 32-pin plcc rtrip1 4 3 2 1 32 31 30 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 d1 hpb hpa vneg rsn 26 27 28 29 ryout1 c2 rye vtx b2en rdcr ryout2 vbat1 e1 c3 d2 nc rdc rtrip2 ringin vcc vbat2 bgnd b(ring) a(tip) rd c1 rsgh rsgl agnd/dgnd notes: 1. pin 1 is marked for orientation. 2. nc = no connect det
am79r79 data sheet 5 pin descriptions pin names type description agnd/dgnd gnd analog and digital ground a(tip) output output of a(tip) power amplifier b2en input vbat2 enable. logic low enables operation from v bat2 . logic high enables operation from v bat1 . ttl compatible. bgnd gnd battery (power) ground b(ring) output output of b(ring) power amplifier c3 ? c1 input decoder. ttl compatible. c3 is msb and c1 is lsb. d1 input relay1 control. ttl compatible. logic low activates the relay1 relay driver. d2 input (option) relay2 control. ttl compatible. logic low activates the relay2 relay driver. det output switchhook detector. logic low indicates that the selected detector is tripped. logic inputs c3 ? c1 and e1 select the detector. open-collector with a built-in 15 k ? pull-up resistor. e1 input (option) ground-key enable. a logic high selects the off-hook detector. a logic low selects the ground-key detector. ttl compatible. hpa capacitor high-pass filter capacitor. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter capacitor. b(ring) side of high-pass filter capacitor. rd resistor detector resistor. detector threshold set and filter pin. rdc resistor dc feed resistor. connection point for the dc feed current programming network, which also connects to the receiver summing node (rsn). v rdc is negative for normal polarity and positive for reverse polarity. rdcr ? connection point for feedback during ringing. ringin input ring signal input. pin for ring signal input. square-wave shaped by external rc filter. requires 50% duty cycle. cmos-compatible input. rsgh input saturation guard high. pin for resistor to adjust open circuit voltage when operating from v bat1 . rsgl input saturation guard low. pin for resistor to adjust the anti-saturation cut-in voltage when operating from both v bat1 and v bat2 . rsn input receive summing node. the metallic current (ac and dc) between a(tip) and b(ring) is equal to 1000 x the current into this pin. the networks that program receive gain, two-wire impedance, and feed resistance all connect to this node. rtrip1 input ring-trip detector. ring-trip detector threshold set and filter pin. rtrip2 input ring-trip detector. ring-trip detector threshold offset (switch to v bat1 ). for power conservation in any nonringing state, this switch is open. rye output common emitter of ryout1/ryout2. emitter output of ryout1 and ryout2. normally connected to relay ground. ryout1 output relay/switch driver. open-collector driver with emitter internally connected to rye. ryout2 output (option) relay/switch driver. open-collector driver emitter internally connected to rye. vbat1 battery battery supply and connection to substrate. vbat2 battery power supply to output amplifiers. connect to off-hook battery through a diode. vcc power positive analog power supply. vneg power negative analog power supply. this pin is the return for the intern vee regulator. vtx output transmit audio. this output is 0.5066 gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
6 am79r79 data sheet absolute maximum ratings storage temperature ......................... ? 55 c to +150 c v cc with respect to agnd/dgnd .......... 0.4 v to +7 v v neg with respect to agnd/dgnd ...... 0.4 v to v bat2 v bat2 ....................................................v bat1 to gnd v bat1 with respect to agnd/dgnd: continuous..................................... +0.4 v to ? 80 v 10 ms ............................................. +0.4 v to ? 85 v bgnd with respect to agnd/dgnd........ +3 v to ? 3 v a(tip) or b(ring) to bgnd: continuous ...............................v bat1 ? 5 v to +1 v 10 ms (f = 0.1 hz) ..................v bat1 ? 10 v to +5 v 1 s (f = 0.1 hz) .....................v bat1 ? 15 v to +8 v 250 ns (f = 0.1 hz) ...............v bat1 ? 20 v to +12 v current from a(tip) or b(ring).....................150 ma ryout1, ryout2 current................................75 ma ryout1, ryout2 voltage ..................... rye to +7 v ryout1, ryout2 transient ................. rye to +10 v rye voltage ........................................ bgnd to v bat1 c3 ? c1, d2 ? d1, e1, b2en, and ringin input voltage ......................... ? 0.4 v to v cc + 0.4 v maximum power dissipation, continuous, t a = 85 c, no heat sink (see note): in 32-pin plcc package..............................1.33 w thermal data: ................................................................ ja in 32-pin plcc package....................... 45 c/w typ note: thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165 c. the device should never see this temperature and operation above 145 c junction temperature may degrade device reliability. see the slic packaging considerations for more information. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature ............................. 0 c to +70 c* v cc ..................................................... 4.75 v to 5.25 v v neg .................................................. ? 4.75 v to v bat2 v bat1 ................................................. ? 40.5 v to ? 75 v v bat2 .................................................... ? 19 v to v bat1 agnd/dgnd.......................................................... 0 v bgnd with respect to agnd/dgnd ........................ ? 100 mv to +100 mv load resistance on vtx to ground .............. 20 k ? min the operating ranges define those limits between which the functionality of the device is guaranteed. * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of production units.
am79r79 data sheet 7 electrical characteristics note: * performance grade description test conditions (see note 1) min typ max unit note transmission performance 2-wire return loss 200 hz to 3.4 khz (test circuit d) 26 db 1, 4, 6 z vtx , analog output impedance 3 20 ? 4 v vtx , analog output offset voltage 0 c to +70 c ? 35 +35 mv ? 40 c to +85 c ? 40 +40 4 z rsn , analog input impedance 1 20 ? overload level, 2-wire and 4-wire, off hook active state 2.5 vpk 2a overload level, 2-wire on hook, r lac = 600 ? 0.88 vrms 2b thd (total harmonic distortion) +3 dbm, bat2 = ? 24 v ? 64 ? 50 db 5 thd, on hook, oht state 0 dbm, r lac = 600 ? bat1 = ? 75 v ? 40 longitudinal performance (see test circuit c) longitudinal to metallic 200 hz to 1 khz ? 1, ? 3* 52 db l-t, l-4 balance normal polarity ? 2, ? 4 63 reverse polarity ? 2 54 normal polarity, ? 40 c to +85 c ? 2, ? 4 58 4 1 khz to 3.4 khz ? 1, ? 3* 52 normal polarity ? 2, ? 4 58 reverse polarity ? 2 54 normal polarity, ? 40 c to +85 c ? 2, ? 4 54 4 longitudinal signal generation 4-l 200 hz to 800 hz normal polarity 42 longitudinal current per pin (a or b) active or oht state 12 28 marms 4 longitudinal impedance at a or b 0 to 100 hz, t a = +25 c 25 ? /pin idle channel noise c-message weighted noise 0 c to +70 c +7 +11 dbrnc ? 40 c to +85 c +12 4 psophometric weighted noise 0 c to +70 c ? 83 ? 79 dbmp ? 40 c to +85 c ? 78 insertion loss and four- to four-wire balance return signal (see test circuits a and b) gain accuracy 4- to 2-wire 0 dbm, 1 khz ? 0.20 0 +0.20 db 3 gain accuracy 2- to 4-wire and 0 dbm, 1 khz ? 6.22 ? 6.02 ? 5.82 4- to 4-wire gain accuracy 4- to 2-wire oht state, on hook ? 0.35 0 +0.35 gain accuracy 2- to 4-wire and 4- to 4-wire oht state, on hook ? 6.37 ? 6.02 ? 5.77 gain accuracy over frequency 300 to 3400 hz 0 c to +70 c ? 0.10 +0.10 relative to 1 khz ? 40 c to +85 c ? 0.15 +0.15 3, 4 gain tracking +3 dbm to ? 55 dbm 0 c to +70 c ? 0.10 +0.10 relative to 0 dbm ? 40 c to +85 c ? 0.15 +0.15 gain tracking 0 dbm to ? 37 dbm 0 c to +70 c ? 0.10 +0.10 oht state, on hook ? 40 c to +85 c ? 0.15 +0.15 +3 dbm to 0 dbm ? 0.35 +0.35 3 group delay 0 dbm, 1 khz 3 s 1, 4, 6
8 am79r79 data sheet electrical characteristics (continued) description test conditions (see note 1) min typ max unit note line characteristics i l , loop-current accuracy i l in constant-current region, b2en = 0 0.915i l i l 1.085i l ma i l , long loops, active state r ldc = 600 ? , rsgl = open 20 21.7 r ldc = 750 ? , rsgl = short 20 i l , accuracy, standby state 0.8i l i l 1.2i l i l = constant-current region t a = 25 c 18 27 39 ? 40 c to +85 c 18 27 4 i l lim active, a and b to ground 55 110 oht, a and b to ground 55 4 i l , loop current, open circuit state r l = 0 100 a i a , pin a leakage, tip open state r l = 0 100 i b , pin b current, tip open state b to ground 34 ma va, standby, ground-start signaling a to ? 48 v = 7 k ? , b to ground = 100 ? ? 7.5 ? 5 v 4 v ab , open circuit voltage 42.8 8 power supply rejection ratio (v ripple = 100 mvrms), active normal state v cc 50 hz to 3400 hz 33 50 db 5 v neg 50 hz to 3400 hz 30 40 v bat1 50 hz to 3400 hz 30 50 v bat2 50 hz to 3400 hz 30 50 power dissipation on hook, open circuit state v bat1 48 100 mw on hook, standby state v bat2 55 80 10 on hook, oht state v bat1 200 300 on hook, active state v bat1 220 350 off hook, standby state v bat1 or v bat2 r l = 300 ? 2000 2800 10 off hook, oht state v bat1 r l = 300 ? 2000 2200 off hook, active state v bat2 r l = 300 ? 550 750 supply currents i cc , open circuit state 3.0 4.5 ma on-hook v cc supply current standby state 3.2 5.5 oht state 6.2 8.0 active state ? normal 6.5 9.0 i neg , open circuit state 0.1 0.2 on-hook v neg supply current standby state 0.1 0.2 oht state 0.7 1.1 active state ? normal 0.7 1.1 i bat , open circuit state 0.45 1.0 on-hook v bat supply current standby state 0.6 1.5 oht state 2.0 4.0 active state ? normal 2.7 5.0 i l v bat1 10v ? r l 400 + ------------------------------------ =
am79r79 data sheet 9 electrical characteristics (continued) relay driver schematic description test conditions (see note 1) min typ max unit note logic inputs (c3 ? c1, d2 ? d1, e1, and b2en) v ih , input high voltage 2.0 v v il , input low voltage 0.8 i ih , input high current ? 75 40 a i il , input low current ? 400 logic output det v ol , output low voltage i out = 0.8 ma, 15 k ? to v cc 0.40 v v oh , output high voltage i out = ? 0.1 ma, 15 k ? to v cc 2.4 ring-trip detector input ring detect accuracy ? 10 +10 % ring signal v ab , ringing bat1 = ? 75 v, ringload = 1570 ? 66 69 vpk 7 v ab ringing offset v ringin = 2.5 v ? 10 0 10 v ? v ab / ? v ringin (ringin gain) 150 180 210 ground-key detector thresholds ground-key resistive threshold b to ground 2 5 10 k ? ground-key current threshold b to ground 11 ma loop detector r lth , loop-resistance detect threshold active, v bat1 ? 20 20 % 9 active, v bat2 ? 20 20 standby ? 12 12 relay driver output (relay1 and 2) v ol , on voltage (each output) i ol = 30 ma +0.25 +0.4 v v ol , on voltage (each output) i ol = 40 ma +0.30 +0.8 4 i oh , off leakage (each output) v oh = +5 v 100 a zener breakover (each output) i z = 100 a 6.6 7.9 v zener on voltage (each output) i z = 30 ma 11 irtd bat1 1 ? rrt1 --------------------------- -24 a + 335 ? = ryout1 bgnd ryout2 bgnd rye
10 am79r79 data sheet notes: 1. unless otherwise noted, test conditions are bat1 = ? 75 v, bat2 = ? 24 v, v cc = +5 v, v neg = ? 5 v, r l = 600 ? , r dc1 = 80 k ? , r dc2 = 20 k ? , r d = 75 k ? , no fuse resistors, c hp = 0.018 f, c dc = 1.2 f, d 1 = d 2 = 1n400x, two-wire ac input impedance (zsl) is a 600 ? resistance synthesized by the programming network shown below. r sgl = open, r sgh = open, r dcr = 2 k ? , r rt1 = 430 k ? , r rt2 = 12 k ? , c rt = 1.5 f, r slew = 100 k ? , c slew = 0.33 f. 2. a. overload level is defined when thd = 1%. b. overload level is defined when thd = 1.5%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that the two-wire ac load impedance matches the programmed impedance. 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 6. group delay can be greatly reduced by using a z t network such as that shown in note 1 above. the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on linecard performance may also be compensated for by synthesizing complex impedance with the qslac or dslac device. 7. 70 vpk provides 50 vrms with a crest factor of 1.25 to a load of 1400 ? with 2 rf = 100, and rline = 70 ? (1570 ? ). 8. open circuit v ab can be modified using rsgh. 9. r d must be greater than 56 k ? . refer to table 2 for typical value of r lt h . 10. lower power is achieved by switching into low-battery state in standby. standby loop current is returned to v bat1 regardless of the battery selected. notes: * only ? 1 and ? 2 performance grade devices support polarity reversal. ** for correct ground-start operation using tip open, v bat1 on-hook battery must be used. table 1. slic decoding (det ) output state c3 c2 c1 2-wire status e1 = 1 e1 = 0 battery selection 0 0 0 0 open circuit ring trip ring trip b2en 1 0 0 1 ringing ring trip ring trip 2 0 1 0 active loop detector ground key 3 0 1 1 on-hook tx (oht) loop detector ground key 4 1 0 0 tip open loop detector ground key b2en = 1** 5 1 0 1 standby loop detector ground key v bat1 6* 1 1 0 active polarity reversal loop detector ground key b2en 7* 1 1 1 oht polarity reversal loop detector ground key rt2 = 150 k ? ct1 = 60 pf rt1 = 150 k ? vtx rsn v rx rrx = 300 k ? ~
am79r79 data sheet 11 table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when com- puting z t , the internal current amplifier pole and any external stray ca- pacitance between vtx and rsn must be taken into account. z rx is connected from v rx to r sn . z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the rdc pin. i loop is the desired loop current in the constant-current region. r dcr1 , r dcr2 , and c dcr form the network connected to the rdcr pin. see applications circuit for these components. c dcr sets the ringing time constant, which can be between 15 s and 150 s. for high battery state r d is the resistor connected from the rd pin to gnd and r lth is the loop-resistance threshold between on-hook and off-hook detection. r d should be greater than 56 k ? to guarantee detection occurs in the standby state. choose the value of r d for high battery state; then use the equation for r lth to find where the threshold is for low battery. loop-threshold detect equations for high battery this is the same equation as for r d above, except solved for r lth . for low battery for low battery, the detect threshold is slightly higher, which avoids os- cillating between states. r lth standby < r lth active v bat1 < r lth active v bat2 , which guaran- tees no unstable states under all operating conditions. this equation shows at what resistance the standby threshold is; it is actually a cur- rent threshold rather than a resistance threshold, which is shown by the vbat dependency. z t 500 z 2win 2r f ? () = z rx z l g 42l ----------- - 1000 z t ? z t 500 z l 2r f + () + -------------------------------------------------- ? = r dc1 r dc2 2500 i loop -------------- - = + r dcr1 r dcr2 + 3000 iringlim --------------------- - = c dc 19 ms r dc1 r dc2 + r dc1 r dc2 --------------------------------- ? = c dcr r dcr1 r dcr2 + r dcr1 r dcr2 ---------------------------------------- ? 150 s = r d r lth 12.67 ? = r lth r d 12.67 ------------ - = r lth r d 11.37 ------------ - = r lth v bat1 10 ? 915 ----------------------------- r d ? 400 2r f ? ? =
12 am79r79 data sheet dc feed characteristics i l (ma) 0 30 50 v ab (volts) 2) v asl 3) v appl 40 30 20 10 5) v apph 4) v ash figure 1. typical v ab vs. i l dc feed characteristics notes: 1. constant-current region: where 2. low battery where r sgl = resistor to gnd, b2en = logic low. anti-sat region: where r sgl = resistor to v cc , b2en = logic low. r sgl to v cc must be greater than 100 k ? . 3. 4. high battery anti-sat region: where r sgh = resistor to gnd, b2en = logic high. where r sgh = resistor to v cc , b2en = logic high. r sgh to v cc must be greater than 100 k ? . 5. r dc r dc1 r dc2 20 k ? 80 k ? 100 k ? = + = + = v bat1 75 v v bat2 24 v ? = , ? = () v ab i l r l 2500 rdc ------------ - r l ; == r l r l =2r f , + v asl 1000 104 10 3 ? r sgl + () ? 6720 10 3 ? 80 r sgl ? () + ----------------------------------------------------------------- - ; = v asl 1000 r sgl 56 10 3 ? ? () ? 6720 10 3 ? 80 r sgl ? () + -------------------------------------------------------------- - ; = v appl 4.17 v asl + = i loopl v appl r dc1 r dc2 + () 600 -------------------------------------- 2 r f r loop ++ ------------------------------------------------------------------------------- = v ash v ashh v asl + = v ashh 1000 70 10 3 ? r sgh + () ? 1934 10 3 ? 31.75 r sgh ? () + ---------------------------------------------------------------------- - ; = v ashh 1000 r sgh 2.75 10 3 ? + () ? 1934 10 3 ? 31.75 r sgh ? () + ---------------------------------------------------------------------- - ; = v apph 4.17 v ash + = i looph v apph r dc1 r dc2 + () 600 -------------------------------------- 2 r f r loop ++ ------------------------------------------------------------------------------ - = high battery anti-sat low battery anti-sat 1) constant-current region
am79r79 data sheet 13 ring-trip components where r lrt = loop-detection threshold resistance for ring trip and cf = crest factor of ringing signal ( 1.25 ) r slew , c slew ring waveform rise time 0.214 ? (r slew ? c slew ) tr. for a 1.25 crest factor @ 20 hz, tr 10 ms. (r slew = 150 k ? , c slew = 0.33 f. ) c slew should be changed if a different crest factor is desired. r rt2 12 k ? = c rt 1.5 f = r rt1 320 cf v bat1 v bat1 5 ? 24 a320cf r lrt 150 2r f ++ () ? ? ? () ? ------------------------------------------------------------------------------------------------------------------------------- ---------- - ? ? r lrt 150 2r f ++ () ? = 0 a(tip) battery figure 2. ringing waveforms b(ring) this is the best time for switching between ringing and other states for minimizing detect switching transients. ringing reference (input to r slew ) a b i l rsn rdc r dc2 r dc1 c dc slic r l a b feed current programmed by r dc1 and r dc2 figure 3. feed programming
14 am79r79 data sheet test circuits r t r rx v ab v l r l 2 i l2-4 = 20 log (v tx / v ab ) a. two- to four-wire insertion loss a(tip) b(ring) agnd vtx rsn slic r t v ab a(tip) b(ring) agnd vtx rsn slic r l r rx v rx i l4-2 = 20 log (v ab / v rx ) brs = 20 log (v tx / v rx ) b. four- to two-wire insertion loss and four- to four-wire balance return signal r t r rx r l 2 r l 2 v rx s1 c s2 v l v l a(tip) b(ring) agnd vtx rsn slic 1 c << r l l-4 long. bal. = ? 20 log (v tx / v l ) l-t long. bal. = ? 20 log (v ab / v l ) 4-l long. sig. gen. = 20 log (v l / v rx ) c. longitudinal balance r l 2 v ab s2 open, s1 closed s2 closed, s1 open
am79r79 data sheet 15 test circuits (continued) v cc a(tip) b(ring) det e1 6.2 k ? r l = 600 ? 15 pf e. loop-detector switching a(tip) b(ring) f. ground-key switching rg d. two-wire return loss test circuit r r return loss = ? 20 log (2 v m / v s ) z d : the desired impedance; e.g., the characteristic impedance of the line v m z in v s a(tip) b(ring) agnd vtx rsn slic r t2 r rx c t1 r t1 z d g. rfi test circuit 50 ? l 1 200 ? 200 ? c 1 c 2 b hf gen vtx a slic under test l 2 c ax 33 nf c bx 33 nf rf 1 rf 2 50 ? 50 ? 1.5 vrms 80% amplitude modulated 100 khz to 30 mhz
16 am79r79 data sheet test circuits (continued) +5 v h. am79r79 test circuit vneg vcc r d rd vtx rsn r rx r dc1 r dc2 c dc r t rdc ? 5 v vbat1 det d 1 bgnd ryout1 hpb c hp hpa rtrip2 rtrip1 a(tip) b(ring) bat1 vbat2 2.2 nf 2.2 nf v tx v rx b2en d 2 bat2 a(tip) b(ring) 0.1 f ryout2 c1 c2 c3 d1 d2 e1 r dcr rdcr agnd/ dgnd r slew c slew ringin r sgh r sgl rsgl rsgh r rt1 r rt2 c rt 1.5 f 75 k ? 12 k ? 430 k ? open 20 k ? 80 k ? 2.0 k ? 100 k ? 1.2 f 0.33 f see note below. c ax c bx 18 nf 300 k ? 300 k ? 0.1 f rye open note: the input should be 50% duty cycle cmos-compatible input. note: refer to applications circuit for recommended configuration. battery ground analog ground digital ground
am79r79 data sheet 17 application circuit note: the input should be 50% duty cycle cmos-compatible input. i. application circuit +5 v vneg vcc r d rd vtx rsn r rx r dc1 r dc2 c dcr r t1 rdc ? 5 v vbat1 det d 1 bgnd ryout1 rtrip2 rtrip1 bat1 vbat2 v tx v rx b2en d 2 bat2 0.1 f ryout2 c1 c2 c3 d1 d2 e1 r dcr1 rdcr agnd/ dgnd r slew c slew ringin r sgh r sgl rsgl rsgh r rt1 r rt2 c rt 1.5 f 66 k ? 12 k ? 515 k ? open 50 k ? 50 k ? 15 k ? 150 k ? 0.33 f see note. 250 k ? 0.1 f rye open 125 k ? 125 k ? c dc r dcr2 15 k ? 820 nf c t r t2 10 nf assumptions: 1. 1.25 cf 2. 25 ma i loop 3. 100 ma ringing current limit 4. 5.2 k ? high battery loop threshold 5. 925 ? ringing loop threshold 6. 600 ? two-wire impedance, 600 ? z l battery ground analog ground digital ground 7. g 42l = 1 8. ?70 v vbat1, ?24 v vbat2 hpb hpa a(tip) b(ring) bat1 tisp 61089 c ax = 2.2 nf k1 k1 k2 k2 g r fa = 50 ? r fb = 50 ? a a c bx = 2.2 nf c hp 18 nf tip ring
18 am79r79 data sheet physical dimensions pl032 revision summary revision b to revision c minor changes were made to the data sheet style and format to conform to legerity standards. electrical characteristics; last row under ring signal, min changed from 130 to 150, typ changed from 160 to 180, and max changed from 190 to 210. slic decoding table; added b2en reference to the battery selection column and its corresponding note to the notes section. applications circuit; revised revision c to revision d minor changes were made to the data sheet style and format to conform to legerity standards. revision d to revision e on pages 17 and 18, r dc1 and r dc2 were switched. revision e to revision f ? the physical dimensions (pl032) were added to the physical dimensions section. ? deleted the ceramic dip and plastic dip packages and references to them. ? updated the pin description table to correct inconsistencies. revision f to revision g ? the equation on page 13 was changed: from: to: .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530 r rt1 300 cf v bat1 vbat 3.5 ? 15 a300cf r lrt 150 2r f ++ () ? ? ? () ? ------------------------------------------------------------------------------------------------------------------------------- ---------- - ? ? r lrt 150 2r f ++ () ? = r rt1 320 cf v bat1 vbat 5 ? 24 a320cf r lrt 150 2r f ++ () ? ? ? () ? ------------------------------------------------------------------------------------------------------------------------------- ------ ? ? r lrt 150 2r f ++ () ? =
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